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[SourceCode] ethernet IP core

Description: ethernet ip core,support100Mbps or 10Mbps
Platform: | Size: 934781 | Author: qhh198833 | Hits:

[SourceCode] Altera IP Core

Description: 15 Altera IP Core
Platform: | Size: 49033 | Author: mayli8 | Hits:

[SCM] mc8051_design

Description: MC8051 IP CoreOregano Systems 8-bit Microcontroller IP-Core此公司提供的8051 core很容易在FPGA 上用同时也是学习VHDL的一份不错的进阶实例-MC8051 IP CoreOregano Systems 8-bit Microcontroller IP-Core company for the 8051 core very easy to use in FPGA VHDL is also studying a good example of the SSP
Platform: | Size: 557056 | Author: 寇锐 | Hits:

[VHDL-FPGA-Verilog] 经典高速乘法器IP

Description: 乘法器是硬件设计中的很常见也很重要的一个模块，它的VHDL硬件实现很好的解决了软件编程中做乘法速度慢的问题，在实时高速系统应用中或DSP软核或数字信号处理硬件实现算法中，经常能使用到乘法器，所以经典的高速乘法器IP 很有参考价值-Multiplier is a common and important module in hardware designing.Its VHDL addresses the low speed of multiplication in software programming. Multiplier is often used in real-time high-speed system application , DSP soft core or hardware implementation of digital signal processing,so it is worthful to know classic high-speed multiplier IP
Platform: | Size: 309248 | Author: czy | Hits:

[VHDL-FPGA-Verilog] tiny16cpu_maxII

Description: 这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核，文档齐全-this is the ALtera devoted second-generation PLD MAXII on the 16-bit microprocessor IP core, complete documentation
Platform: | Size: 240640 | Author: 李无志 | Hits:

[USB develop] usb_doc

Description: USB IP core.very good
Platform: | Size: 142336 | Author: 张卫 | Hits:

[VHDL-FPGA-Verilog] Synopsys

Description: Synopsys 8051 IP core documentation.
Platform: | Size: 1176576 | Author: | Hits:

[VHDL-FPGA-Verilog] I2C_IPcore_VHDL

Description: 这是一个I2C串行数据通信协议以VHDL硬件描述语言实现的IP核，可直接编译运行-I2C serial data communication protocol to VHDL hardware description language of the IP core can be directly translated Operation
Platform: | Size: 6144 | Author: 陈州徽 | Hits:

[ARM-PowerPC-ColdFire-MIPS] Altera的IP源码8237

Description: 名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-renowned name of the company Synopsys 8051IP Core VHDL language, support can be keilC51
Platform: | Size: 207872 | Author: 上面的 | Hits:

[VHDL-FPGA-Verilog] sARM7TM

Description: ARM7TM core源码，此码来自于opencore组织，此组织免费提供一些IP core，都是一些老外写的。-ARM7TM core source, the code from opencore organizations, this organization provided free IP core, are written by foreigners.
Platform: | Size: 70656 | Author: | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARM_Core

Description: arm verilog hdl ip core-arm Verilog HDL core ip
Platform: | Size: 70656 | Author: lile | Hits:

[SCM] mc8051

Description: fpga 8051单片机IP核。This is version 1.3 of the MC8051 IP core-8051 IP core. This is version 1.3 of the IP core MC8051
Platform: | Size: 302080 | Author: 周仕凤 | Hits:

[Driver Develop] ata_ip

Description: ATA接口的IP核,经过量产的验证,已经在quartus5.1下编译通过了.-ATA interface IP core, after volume production test in quartus5.1 compiler passed.
Platform: | Size: 510976 | Author: 李想 | Hits:

[Driver Develop] wb_dma.tar

Description: DMA的控制器的IP核,和ATA控制器配合,可以实现DMA方式高速传输数据.-DMA controller IP core, and ATA controller tie, DMA can achieve high-speed transmission of data.
Platform: | Size: 143360 | Author: 李想 | Hits:

[VHDL-FPGA-Verilog] user_logic_VGA_Controller

Description: user_logic_VGA_Controller，适合于DE2开发板，把这个文件夹放在工程目录之中，就可以在SOPC里直接添加VGA_Controller IP核了，很方便使用。-user_logic_VGA_Controller. suitable for Dictyophora development board, this folder on the project directory, it can be added directly SOPC Lane VGA_Controller IP core, very convenient to use.
Platform: | Size: 70656 | Author: 曾 | Hits:

[Documents] DES_IP

Description: 是VDKL语言实现的DES算法，是一个IP核， 对于相关方面有很好的帮助-VDKL language of the DES algorithm is an IP core, related well with the help of
Platform: | Size: 174080 | Author: 小四 | Hits:

[VHDL-FPGA-Verilog] adma

Description: Wishbone dma ip core
Platform: | Size: 7168 | Author: liwen | Hits:

[Software Engineering] DesignofTrainCommunicationAdapterBasedonSOPC

Description: 介绍了MVB总线帧结构，并完成了用于网络连接的MVB总线访问IP核的设计。-introduced the MVB bus frame structure, and completed the network connection for the MVB bus visit IP core design.
Platform: | Size: 149504 | Author: 阿康 | Hits:

[Other] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Platform: | Size: 359424 | Author: 任学 | Hits:

[Other] ptc

Description: PWM/TIMER/COUNTER VHDL IP core
Platform: | Size: 272384 | Author: hehilon | Hits:
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